1. Field of the Invention
The present invention relates to D-type latch circuits, and more particularly to a D-type latch circuit suitably adapted to a decision circuit of a receive part in an optical fiber communication system or a comparator of a high-speed A/D (analog-to-digital) converter.
2. Description of the Related Art
FIG. 1 is a circuit diagram of a conventional D-type latch circuit, which includes differential amplifier circuits 1 and 2. The differential amplifier circuit 1 includes enhancement-type MES FETs 3 and 4, which perform a differential amplifying operation on complementary input signals IN and /IN. The term "MES FET" is an abbreviation of metal-semiconductor field effect transistor. The differential amplifier circuit 2 includes enhancement-type MES FETs 5 and 6, which perform a differential amplifying operation on complementary output signals OUT and /OUT.
A resistor 7 is a load of the MES FETs 3 and 5, and a resistor 8 is a load of the MES FETs 4 and 6. The differential amplifier circuit 1 includes an enhancement-type MES FET 9, which conducts (ON) and non-conducts (OFF) according to a transfer signal TR. The differential amplifier circuit 2 includes an enhancement-type MES FET 10, which is turned ON and OFF according to a latch signal LT. A depletion-type MES FET 11 functions as a constant-current source of the differential amplifier circuits 1 and 2.
The D-type latch circuit shown in FIG. 1 further includes an output circuit 12 including a source-follower circuit. The output circuit 12 includes enhancement-type MES FETs 13 and 14 serving as output transistors, and depletion-type MES FETs 15 and 16 serving as constant-current sources.
FIG. 2 is a waveform diagram of an operation of the D-type latch circuit shown in FIG. 1, and more particularly shows waveforms of the input signals IN, /IN, the output signals OUT and /OUT, the transfer signal TR and the latch signal LT.
When the transfer signal TR is at a high level (H) and the latch signal LT is at a low level (L), the MES FET 9 is ON and the MES FET 10 is OFF. Further, the differential amplifier circuit 1 is in an active state, and the differential amplifier circuit 2 is in an inactive state. Hence, the D-type latch circuit performs a transfer operation on the input signals IN and /IN by the differential amplifier circuit 1 and the output circuit 12.
In the above case, when the input signals IN and /IN are respectively at the low and high levels, the MES FETs 3 and 4 are respectively OFF and ON. Further, the levels of nodes 17 and 18 shown in FIG. 1 are respectively high and low, and the MES FETs 13 and 14 are respectively OFF and ON. Hence, the output signals OUT and /OUT are respectively at the low and high levels.
In the above state, when the transfer signal TR switches to the low level and the latch signal LT switches to the high level, the MES FETs 9 and 10 are respectively turned OFF and ON, and the differential amplifier circuits 1 and 2 are switched to the inactive and active states, respectively. Hence, the D-type latch circuit performs a latch operation on the input signals IN and /IN by the output circuit 12 and the differential amplifier circuit 2.
The input signals IN and /IN are transferred to the differential amplifier circuit 2 via the output circuit 12 from the differential amplifier circuit 1. Hence, when the states of the input signals IN and /IN change, the output signals OUT and /OUT are changed with a delay time t.sub.SU -A caused by the differential amplifier circuit 1, the output circuit 12 and the differential amplifier circuit 2. Hence, in order to latch the transitions of the states of the input signals IN and /IN in the D-type latch circuit, it is necessary to fall the transfer signal TR and rise the latch signal LT when the delay time t.sub.SU -A elapses after the transitions of the states of the input signals.
In other words, it is not possible to latch the transitions of the input signals IN and /IN unless the delay time t.sub.SU -A elapses from the transitions of the input signals IN and /IN. The above fact prevents applications of the D-type latch circuit to high-speed circuits, such as a decision circuit in a receive part in an optical fiber communication system and a comparator in an A/D converters. The decision circuit determines whether the received signal is "1" or "0".
Further, the D-type latch circuit shown in FIG. 1 is greatly affected by deviations of the threshold voltages of the transistors used therein caused by factors in the production process. In other words, the D-type latch circuit does not have any means for reducing the influence of the deviations of the threshold voltages of the transistors.